The invention is based on a priority application EP 04 293 126.1 which is hereby incorporated by reference.
The present invention is directed to a redundant synchronous clock distribution system, comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system, wherein each of the first and second clock modules is adapted to act, in a master mode, as a master clock module for providing one of the clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of the clock distribution branches with a standby clock signal.
In order to perform an effective data exchange in e.g. a telecommunication system or network, a control mechanism is necessary which allows for the data transmission to be compliant with certain defined data communication conventions. For example, data transmission in a telecommunications network may be performed synchronously or asynchronously. Telecommunication networks which work in interconnection with standardized communication networks such as PDH, SDH, or Sonet, usually require synchronization to assure the required signal quality at the data interface. In this context, redundant synchronous clock distribution systems are used to provide the required clock reference signal.
A redundant synchronous clock distribution system typically comprises two clock boards. One operates as the master clock board while the other operates as a slave clock board. Each of the clock boards has a plurality of reference clock inputs, each provisioning both clock modules with a certain reference clock signal. Both clock boards further comprise an input selector module that is adapted to select a reference clock signal from the plurality of reference clock signals provisioned at the inputs of the clock boards. Under software control both boards select a similar clock reference so that they both derive the same clock signal for provisioning a clean clock-signal to a number of to be synchronised clock slave modules such as a microprocessor board or telecom boards like there are line termination boards, route servers or switch matrix boards. Each input selector module of the boards subsequently is coupled to a timing unit, such as a Sonet timing unit, for generating a “clean” clock signal by jitter and wander clean-up and for provisioning hitless switchover of the selected clock signal. Furthermore each of the clock boards comprises an output selector module for selecting the “clean” clock signal from either clock board A or clock board B. Both clock boards select one and the same of both “clean” clock signals for provisioning the clock signal to the to be clock slave modules. This is usually performed under software control. The clock board that selects its own “clean” clock signal is called the master clock board, while the clock board that selects the “clean” clock signal from the other board is called the slave clock board.
In such redundant synchronous clock distribution system, where all distributed clocks originate from the same clock source, in case of failure of the master clock, a switchover of the clock source in the master and the slave clock distribution board must be performed.
In existent systems, consistency of the output clock selection multiplexers is controlled by software by means of master and slave states. The latency of the software and the communication between the two redundant clock boards will in some cases exceed the maximum allowed time. This is especially true after a switch over from external references while the clock board's PLLs are locking onto the new clock reference. Due to the very low cut off frequency seen in, e.g., Stratum 3, and better clock systems, the time until the differential wander between the PLLs present on each board is sufficiently small to perform a safe multiplexer switch over under software control can take up to several hours after the external reference (or reference phase, or frequency jump, or phase build out) switches over. If this time gets too long, the differential wander causes the system to go down.
An object of the present invention is to provide a redundant synchronous clock distribution system which can provide an improved switchover behaviour in order to improve the availability performance of the clock distribution system.
This object is solved by a redundant synchronous clock distribution system according to claim 1.